In a nonvolatile semiconductor memory device including floating gates as charge storage layers, the memory cell size and the chip size can be shrunk by miniaturization techniques. As the memory cell size and the chip size become smaller in such a nonvolatile semiconductor memory device, peripheral circuit parts such as sense amplifiers become smaller in size. For example, in a case where the device region width (hereinafter also referred to as the “AA width”) in a memory cell part is reduced, circuit devices such as transistors in the peripheral circuit parts are also made smaller, and the distance between these circuit devices is made shorter.
On the other hand, interconnect layers are disposed above the circuit devices on the peripheral circuit parts. To connect these circuit devices to one another, each interconnect layer includes a certain number or more of interconnects (interconnect patterns) in a certain area. However, when the AA width in the memory cell part is made smaller, it becomes to provide the interconnects at a higher density in the peripheral circuit parts, and therefore the distance between the interconnects in each interconnect layer becomes shorter. Due to this, there is a probability that short circuiting is generated between the interconnects in each interconnect layer. Therefore, a further reduction of the size of each peripheral circuit part is realized by reducing the number of interconnects placed on the peripheral circuit parts.
JP-A 2007-234878 (KOKAI) discloses an example of a planar shape and a sectional shape of a device region of a switching device, which is provided in a peripheral circuit part placed in the periphery of a memory cell part.